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1/16 ? semiconductor MSM5116165B description the MSM5116165B is a 1,048,576-word 16-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the MSM5116165B achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/double-layer metal cmos process. the MSM5116165B is available in a 42-pin plastic soj or 50/44-pin plastic tsop. features ? 1,048,576-word 16-bit configuration ? single 5 v power supply, 10% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 4096 cycles/64 ms ? fast page mode with edo, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? package options: 42-pin 400 mil plastic soj (soj42-p-400-1.27) (product : MSM5116165B-xxjs) 50/44-pin 400 mil plastic tsop (tsopii50/44-p-400-0.80-k) (product : MSM5116165B-xxts-k) (tsopii50/44-p-400-0.80-l) (product : MSM5116165B-xxts-l) xx indicates speed rank. product family ? semiconductor MSM5116165B 1,048,576-word 16-bit dynamic ram : fast page mode type with edo MSM5116165B-70 70 ns 130 ns 90 ns 440 mw 550 mw family access time (max.) cycle time (min.) standby (max.) power dissipation MSM5116165B-50 t rac 50 ns 35 ns t aa 25 ns 20 ns t cac 13 ns 20 ns t oea 13 ns MSM5116165B-60 60 ns 110 ns 495 mw 30 ns 15 ns 15 ns operating (max.) 5.5 mw e2g0053-17-41 this version: jan. 1998 previous version: may 1997
2/16 ? semiconductor MSM5116165B pin configuration (top view) a9r a8r a7 a6 a5 a4 a11r a10r a0 a1 a2 a3 a9r a8r a7 a6 a5 a4 a11r a10r a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 21 22 30 31 32 33 34 35 36 37 38 39 40 41 42 v cc dq1 dq2 dq3 dq4 v cc dq5 dq6 dq7 dq8 nc nc we v cc v ss ucas lcas nc dq9 dq10 dq11 dq12 v ss dq13 dq14 dq15 dq16 v ss 14 29 ras oe 15 28 a11r a9r 16 27 a10r a8r 17 26 a0 a7 18 25 a1 a6 19 24 a2 a5 20 23 a3 a4 1 2 3 4 5 6 7 8 9 10 11 25 26 40 41 42 43 44 45 46 47 48 49 50 v cc dq1 dq2 dq3 dq4 v cc dq5 dq6 dq7 dq8 nc v cc v ss nc dq9 dq10 dq11 dq12 v ss dq13 dq14 dq15 dq16 v ss 15 36 nc nc 16 35 nc lcas 17 34 we ucas 18 33 ras oe 19 32 20 31 21 30 22 29 23 28 24 27 1 2 3 4 5 6 7 8 9 10 11 25 26 40 41 42 43 44 45 46 47 48 49 50 v cc dq1 dq2 dq3 dq4 v cc dq5 dq6 dq7 dq8 nc v cc v ss nc dq9 dq10 dq11 dq12 v ss dq13 dq14 dq15 dq16 v ss 15 36 nc nc 16 35 nc lcas 17 34 we ucas 18 33 ras oe 19 32 20 31 21 30 22 29 23 28 24 27 42-pin plastic soj 50/44-pin plastic tsop (k type) 50/44-pin plastic tsop (l type) note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. pin name function a0 - a7, address input ras row address strobe lcas lower byte column address strobe dq1 - dq16 data input/data output oe output enable we write enable v cc power supply (5 v) nc no connection a8r - a11r ucas upper byte column address strobe v ss ground (0 v)
3/16 ? semiconductor MSM5116165B block diagram timing generator refresh control clock column address buffers internal address counter row address buffers row deco- ders word drivers memory cells sense amplifiers column decoders i/o controller i/o controller i/o selector input buffers output buffers output buffers input buffers on chip v bb generator v cc dq1 - dq8 dq9 - dq16 ucas we a0 - a7 8 16 8 8 16 88 88 8 8 12 oe ras lcas 8 8 4 a8r - a11r on chip iv cc generator v ss function table function mode ras h l input pin lcas * h l ucas h we h h h l l oe l l l h l l l l l h l l h l l h l * * * * * h lower byte read upper byte read word read refresh standby lower byte write dq pin dq1 - dq8 high-z high-z d out d in dq9 - dq16 high-z high-z high-z d out don't care high-z d out d out don't care d in upper byte write l lll h d in d in word write h lll h high-z high-z h *: "h" or "l"
4/16 ? semiconductor MSM5116165B electrical characteristics absolute maximum ratings voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v in , v out symbol i os p d * t opr t stg C0.5 to v cc + 0.5 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit voltage on v cc supply relative to v ss v cc C0.5 to 7 v recommended operating conditions *: ta = 25 c power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.5 0 2.4 C0.5 *2 min. 5.5 0 v cc + 0.5 *1 0.8 max. (ta = 0c to 70c) v unit v v v notes : *1. the input voltage is v cc + 2.0 v when the pulse width is less than 20 ns (the pulse width is with respect to the point at which v cc is applied). *2. the input voltage is v ss C 2.0 v when the pulse width is less than 20 ns (the pulse width is with respect to the point at which v ss is applied). capacitance input capacitance (a0 - a7, a8r - a11r) input capacitance output capacitance (dq1 - dq16) c in1 symbol c in2 c i/o 5 7 7 max. pf unit pf pf parameter (v cc = 5 v 10%, ta = 25c, f = 1 mhz) typ. ( ras , lcas , ucas , we , oe )
5/16 ? semiconductor MSM5116165B dc characteristics notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih . i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o 5.5 v ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) dq = enable average power cas before ras supply current ( cas before ras refresh) ras = v il , average power cas cycling, supply current t hpc = min. (fast page mode) v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 3 v cc C0.2 v ras cycling, parameter condition msm5116165 b-50 msm5116165 b-60 msm5116165 b-70 (v cc = 5 v 10%, ta = 0c to 70c) symbol min. 2.4 0 C10 C10 max. v cc 0.4 10 10 100 2 1 100 100 90 5 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 90 2 1 90 90 80 5 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 80 2 1 80 80 70 5 unit v v m a m a ma ma ma ma ma ma note 1, 2 1, 2 1, 2 1, 3 1 1
6/16 ? semiconductor MSM5116165B ac characteristics (1/2) parameter msm5116165 b-60 msm5116165 b-70 msm5116165 b-50 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3 random read or write cycle time read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from cas precharge cas to data output buffer turn-off delay time transition time ras precharge time ras pulse width ras pulse width (fast page mode with edo) ras hold time cas pulse width cas hold time ras to cas delay time ras to column address delay time cas to ras precharge time row address set-up time row address hold time column address set-up time column address hold time column address to ras lead time access time from oe oe to data output buffer turn-off delay time refresh period ras hold time referenced to oe unit min. max. min. max. ras hold time from cas precharge symbol t rc t rwc t hpc t hprwc t rac t cac t aa t cpa t cez t t t rp t ras t rasp t rsh t cas t csh t rcd t rad t crp t asr t rah t asc t cah t ral t oea t oez t ref t roh t rhcp note min. max. output low impedance time from cas t clz cas precharge time (fast page mode with edo) t cp 4, 5, 6 4, 5 4, 6 4, 13 7, 8 15 5 6 13 12 12 4 7 4 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 84 110 20 58 0 0 1 30 50 50 7 7 7 35 11 9 5 0 7 0 7 25 0 7 30 50 13 25 30 13 50 10,000 100,000 10,000 37 25 13 13 64 124 160 30 78 0 0 1 50 70 70 13 10 13 45 14 12 5 0 10 0 13 35 0 13 40 70 20 35 40 20 50 10,000 100,000 10,000 50 35 20 20 64 104 135 25 68 0 0 1 40 60 60 10 10 10 40 14 12 5 0 10 0 10 30 0 10 35 60 15 30 35 15 50 10,000 100,000 10,000 45 30 15 15 64 data output hold after cas low we to data output buffer turn-off delay time ras to data output buffer turn-off delay time t doh t wez t rez 7, 8 7 ns ns ns 5 5 5 oe hold time from cas (dq disable) t cho ns 5 5 5 0 0 13 13 0 0 20 20 0 0 15 15 13
7/16 ? semiconductor MSM5116165B ac characteristics (2/2) msm5116165 b-60 msm5116165 b-70 msm5116165 b-50 write command pulse width write command to cas lead time write command to ras lead time data-in set-up time cas to we delay time ras to we delay time column address to we delay time ras to cas hold time ( cas before ras ) cas active delay time from ras precharge data-in hold time write command hold time oe command hold time oe to data-in delay time (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3 write command set-up time t wp t cwl t rwl t ds t cwd t rwd t awd t chr t rpc t dh t wch t oeh t oed t wcs min. max. parameter symbol unit note min. max. min. max. ras to cas set-up time ( cas before ras )t csr cas precharge we delay time t cpwd 14 11, 12 10 10 10 12 13 12 11, 12 12 10, 12 10 10 10 10 0 34 79 49 5 10 5 10 10 10 15 0 54 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 7 7 0 30 67 42 5 10 5 7 7 7 13 0 47 10 13 13 0 44 94 59 5 10 5 13 13 13 20 0 64 read command set-up time read command hold time read command hold time referenced to ras t rcs t rch t rrh 12 9, 12 9 ns ns ns 0 0 0 0 0 0 0 0 0 we pulse width (dq disable) t wpe 10 ns 7 10 oe command hold time t och 10 ns 7 10 oe precharge time t oep 10 ns 7 10
8/16 ? semiconductor MSM5116165B notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 2 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl loads and 100 pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t cez (max.), t rez (max.), t wez (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t cez and t rez must be satisfied for open circuit condition. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. these parameters are referenced to the ucas and lcas , leading edges in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle. 12. these parameters are determined by the falling edge of either ucas or lcas , whichever is earlier. 13. these parameters are determined by the rising edge of either ucas or lcas , whichever is later. 14. t cwl should be satisfied by both ucas and lcas . 15. t cp is determined by the time both ucas and lcas are high.
9/16 ? semiconductor MSM5116165B "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t ds t dh valid data-in t wp t ral open t rwl t cwl "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t cez open t clz valid data-out t rez timing waveform read cycle write cycle (early write) e2g0098-17-41k
10/16 ? semiconductor MSM5116165B "h" or "l" ras cas v ih v il C C v ih v il C C dq v i/oh v i/ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rwc t ras t rp t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh read modify write cycle
11/16 ? semiconductor MSM5116165B fast page mode read cycle (part-1) fast page mode read cycle (part-2) C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cp t cah t asc t rad t rcs t rch t rac t aa t cac t clz t wez t oea valid data-out valid data-out valid data-out t rah t asr t cah t asc t cah t asc t cac t aa t doh t cez t cpa t aa t cac t rcs t wpe t rhcp e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cah t asc t rad t rcs t aa t rrh t cac t clz t cpa t oea valid data-out valid* data-out t rah t asr t cah t asc t cah t asc t rac valid data-out t aa t cac t doh valid* data-out t cac t rez t oez t oez t cho t och t aa t oea t oep t oep t oea * : same data, t cp t rhcp
12/16 ? semiconductor MSM5116165B fast page mode write cycle (early write) fast page mode read modify write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol t asr row column t rasp t cwd t rah column t rcd t cp t asc t cah t cpa t asc t rad t rwd "h" or "l" valid data-out t oez t oed t ds t wp t awd t rcs t cwd t rwl t cac t awd t rac t wp t clz t dh t oeh valid data-in t oea valid data-out t oez t oed t cac t dh t oeh valid data-in t oea t clz t ds t aa t aa t rcs t cah t cpwd t hprwc t crp t cwl e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il t asr row column t crp t rp t rasp t cas t csh t rah column column t rcd t cp t cas t cas t hpc t cp t hpc t asc t cah t cah t cah t asc t asc t rad "h" or "l" t dh t ds t wch valid data-in t ds t dh t ds t dh t wch t wch t rsh valid data-in valid data-in t wcs t wcs t wcs
13/16 ? semiconductor MSM5116165B ras -only refresh cycle ras cas v ih v il C C v ih v il C C address v ih v il C C t rc t ras t rp t crp t rpc t asr t rah row "h" or "l" dq v oh v ol e e note: we , oe = "h" or "l" t cez open cas before ras refresh cycle ras cas v ih v il C C v ih v il C C t chr note: we , oe , address = "h" or "l" dq v oh v ol C C t rc t rp t ras t rp t rpc t cp t csr t rpc t cez open
14/16 ? semiconductor MSM5116165B hidden refresh read cycle hidden refresh write cycle ras cas address oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C "h" or "l" we v ih v il C C dq v oh v ol C C t rc t rc t ras t rp t ras t rp t crp t rcd t rsh t chr t rad t asr t rah t asc t cah row column t rcs t ral t rrh t aa t roh t oea t cac t rac t clz t oez valid data-out open e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il "h" or "l" t asr row column t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral t rwl t chr t ras t rc t rp t ds t wp t wch t dh valid data-in t wcs
15/16 ? semiconductor MSM5116165B (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj42-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.86 typ. mirror finish
16/16 ? semiconductor MSM5116165B (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.60 typ. tsop ii 50/44-p-400-0.80-k mirror finish

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